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module registerCouner(rld,dec,load,di,clk,do);
  input rld,dec,load,clk;
  input [11:0]di;
  
  output reg [11:0]do;
  reg [11:0]out_next;
  wire pl=load|(~rld);
  always @(posedge clk)
    casex({load,dec})
      3'b1x:do=di;
      3'bx1:do=do-1;
    endcase
endmodule

module zeroDetector(di,req);
  input [11:0] di;
  output  req;
  assign req=(di===11'h0)?1'b1:1'b0;
endmodule

module stackPointer(push,pop,clear,clk,do,full);
  input push,pop,clear,clk;
  output reg full;
  reg empty;
  output reg [2:0]do;
  reg [2:0] out_next;
  always @(posedge clk)
  begin 
  casex({push,pop,clear}) 
   3'b100:
   begin
     if(do==3'h7)
       begin
       do<=do;
       full<=1'b1;
      end
     else
       begin
         full<=1'b0;
       if(empty==1'b1)
         begin
         do<=do+1;
         empty<=1'b0;
        end
      else
       do<=do+1;
     end
   end
   3'b010:
   begin
     full<=1'b0;
    if(empty==1'b0)
      if(do==3'b0)
        begin
        do<=do;
        empty<=1'b1;
        end
      else 
        do<=do-1;
    end
    3'b001:
      begin
        full<=1'b0;
        do<=3'b000;
        empty<=1'b1;
      end
    
  endcase
end
  endmodule
  
  module instrDecoder(instr,cc,RZero,plrc,dec,clear,push,pop,respc,selmux,pln,mapn,vectn);
    input [3:0] instr; 
    input cc,RZero;
    output reg plrc,dec,clear,push,pop,respc,pln,mapn,vectn;
    output reg [1:0] selmux;
    
    always @(instr or cc or RZero)
    begin
      casex({instr,cc,RZero})
        6'b0000_x_x: begin plrc=1'b0;dec=1'b0;clear=1'b1;push=1'b0;pop=1'b0;respc=1'b1;selmux=2'b11;pln=1'b0;mapn=1'b1;vectn=1'b1; end
        
        6'b0001_1_x:begin plrc=1'b0;dec=1'b0;clear=1'b0;push=1'b0;pop=1'b0;respc=1'b0;selmux=2'b11;pln=1'b0;mapn=1'b1;vectn=1'b1;end
        
        6'b0001_0_x: begin plrc=1'b0;dec=1'b0;clear=1'b0;push=1'b1;pop=1'b0;respc=1'b0;selmux=2'b00;pln=1'b0;mapn=1'b1;vectn=1'b1;end
        
        6'b0010_x_x:begin plrc=1'b0;dec=1'b0;clear=1'b0;push=1'b0;pop=1'b0;respc=1'b0;selmux=2'b00;pln=1'b1;mapn=1'b0;vectn=1'b1;end
        
        6'b0011_1_x: begin plrc=1'b0;dec=1'b0;clear=1'b0;push=1'b0;pop=1'b0;respc=1'b0;selmux=2'b11;pln=1'b0;mapn=1'b1;vectn=1'b1;end
        
        6'b0011_0_x:begin plrc=1'b0;dec=1'b0;clear=1'b0;push=1'b0;pop=1'b0;respc=1'b0;selmux=2'b00;pln=1'b0;mapn=1'b1;vectn=1'b1;end
        
        6'b0100_1_x:begin plrc=1'b0;dec=1'b0;clear=1'b0;push=1'b1;pop=1'b0;respc=1'b0;selmux=2'b11;pln=1'b0;mapn=1'b1;vectn=1'b1;end
        
        6'b0100_0_x:begin plrc=1'b1;dec=1'b0;clear=1'b0;push=1'b1;pop=1'b0;respc=1'b0;selmux=2'b11;pln=1'b0;mapn=1'b1;vectn=1'b1;end
        
        6'b0101_1_x:begin plrc=1'b0;dec=1'b0;clear=1'b0;push=1'b1;pop=1'b0;respc=1'b0;selmux=2'b01;pln=1'b0;mapn=1'b1;vectn=1'b1;end
        
        6'b0101_0_x:begin plrc=1'b0;dec=1'b0;clear=1'b0;push=1'b1;pop=1'b0;respc=1'b0;selmux=2'b00;pln=1'b0;mapn=1'b1;vectn=1'b1;end
        
        6'b0110_1_x:begin plrc=1'b0;dec=1'b0;clear=1'b0;push=1'b0;pop=1'b0;respc=1'b0;selmux=2'b11;pln=1'b0;mapn=1'b1;vectn=1'b1;end
        
        6'b0110_0_x:begin plrc=1'b0;dec=1'b0;clear=1'b0;push=1'b0;pop=1'b0;respc=1'b0;selmux=2'b00;pln=1'b1;mapn=1'b1;vectn=1'b0;end
        
        6'b0111_1_x:begin plrc=1'b0;dec=1'b0;clear=1'b0;push=1'b0;pop=1'b0;respc=1'b0;selmux=2'b01;pln=1'b0;mapn=1'b1;vectn=1'b1;end
        
        6'b0111_0_x:begin plrc=1'b0;dec=1'b0;clear=1'b0;push=1'b0;pop=1'b0;respc=1'b0;selmux=2'b00;pln=1'b0;mapn=1'b1;vectn=1'b1;end
        
        6'b1000_x_1:begin plrc=1'b0;dec=1'b1;clear=1'b0;push=1'b0;pop=1'b0;respc=1'b0;selmux=2'b10;pln=1'b0;mapn=1'b1;vectn=1'b1;end
        
        6'b1001_x_0: begin plrc = 1'b0; dec = 1'b1; clear = 1'b0; push = 1'b0; pop = 1'b0;respc = 1'b0; selmux = 2'b00; pln = 1'b0; mapn = 1'b1; vectn = 1'b1; end   
        6'b1001_x_1: 
      begin
        plrc = 1'b0; dec = 1'b0; clear = 1'b0; push = 1'b0; pop = 1'b0;
        respc = 1'b0; selmux = 2'b11; pln = 1'b0; mapn = 1'b1; vectn = 1'b1;    
      end
    6'b1010_1_x: 
      begin
        plrc = 1'b0; dec = 1'b0; clear = 1'b0; push = 1'b0; pop = 1'b0;
        respc = 1'b0; selmux = 2'b11; pln = 1'b0; mapn = 1'b1; vectn = 1'b1;    
      end
    6'b1010_0_x: 
      begin
        plrc = 1'b0; dec = 1'b0; clear = 1'b0; push = 1'b0; pop = 1'b1;
        respc = 1'b0; selmux = 2'b10; pln = 1'b0; mapn = 1'b1; vectn = 1'b1;    
      end
    6'b1011_1_x: 
      begin
        plrc = 1'b0; dec = 1'b0; clear = 1'b0; push = 1'b0; pop = 1'b0;
        respc = 1'b0; selmux = 2'b11; pln = 1'b0; mapn = 1'b1; vectn = 1'b1;    
      end
    6'b1011_0_x: 
      begin
        plrc = 1'b0; dec = 1'b0; clear = 1'b0; push = 1'b0; pop = 1'b1;
        respc = 1'b0; selmux = 2'b00; pln = 1'b0; mapn = 1'b1; vectn = 1'b1;    
      end
    6'b1100_x_x: 
      begin
        plrc = 1'b1; dec = 1'b0; clear = 1'b0; push = 1'b0; pop = 1'b0;
        respc = 1'b0; selmux = 2'b11; pln = 1'b0; mapn = 1'b1; vectn = 1'b1;    
      end
    6'b1101_1_x: 
      begin
        plrc = 1'b0; dec = 1'b0; clear = 1'b0; push = 1'b0; pop = 1'b1;
        respc = 1'b0; selmux = 2'b10; pln = 1'b0; mapn = 1'b1; vectn = 1'b1;    
      end
    6'b1101_0_x: 
      begin
        plrc = 1'b0; dec = 1'b0; clear = 1'b0; push = 1'b0; pop = 1'b0;
        respc = 1'b0; selmux = 2'b11; pln = 1'b0; mapn = 1'b1; vectn = 1'b1;    
      end
    6'b1110_x_x: 
      begin
        plrc = 1'b0; dec = 1'b0; clear = 1'b0; push = 1'b0; pop = 1'b0;
        respc = 1'b0; selmux = 2'b11; pln = 1'b0; mapn = 1'b1; vectn = 1'b1;    
      end
    6'b1111_1_0: 
      begin
        plrc = 1'b0; dec = 1'b1; clear = 1'b0; push = 1'b0; pop = 1'b0;
        respc = 1'b0; selmux = 2'b10; pln = 1'b0; mapn = 1'b1; vectn = 1'b1;    
      end
    6'b1111_0_0: 
      begin
        plrc = 1'b0; dec = 1'b1; clear = 1'b0; push = 1'b0; pop = 1'b1;
        respc = 1'b0; selmux = 2'b11; pln = 1'b0; mapn = 1'b1; vectn = 1'b1;    
      end
    6'b1111_1_1: 
      begin
        plrc = 1'b0; dec = 1'b0; clear = 1'b0; push = 1'b0; pop = 1'b1;
        respc = 1'b0; selmux = 2'b00; pln = 1'b0; mapn = 1'b1; vectn = 1'b1;    
      end
    6'b1111_0_1: 
      begin
        plrc = 1'b0; dec = 1'b0; clear = 1'b0; push = 1'b0; pop = 1'b1;respc = 1'b0; selmux = 2'b11; pln = 1'b0; mapn = 1'b1; vectn = 1'b1;
      end
    endcase
  end
  endmodule
  
 module multiplexer(pc, f, r, d, select, dout);
  input [11:0] pc, f, r, d;
  input [1:0] select;
  output reg [11:0] dout;
  
  always @(pc or f or r or d or select)
    case(select)
      2'b00: dout <= d;
      2'b01: dout <= r;
      2'b10: dout <= f;
      2'b11: dout <= pc;
    endcase
endmodule

module spram8x12(clk,di,do,address,we);
  input[11:0] di;
  input clk, we;
  input[2:0] address;
  output[11:0] do;
  reg[11:0] do;
  reg[11:0] mem[0:7];
  [email protected](posedge clk)
    begin
      do <= mem[address];
      if(we)
        mem[address] <= di;
      end
endmodule


module wordStack(di,clk,push,pop,clear,stackPointer,do);
  input [11:0]di;
  input clk,pop,clear,push;
  input [2:0]stackPointer;
  output  [11:0]do;
  reg we;
  
  spram8x12 spram(clk,di,do,stackPointer,we);
  
  always @(push or pop)
  begin 
    if(push==1'b1)
      we<=1'b1;
    else
      we<=1'b0;
  end
endmodule


module microUpc(clk,clear,di,ci,stackIn,Upc);
  input clk,clear,ci;
  input [11:0] di;
  output reg [11:0] Upc;
  output  [11:0] stackIn;
  always @(posedge clk)
  begin 
    if(clear===1'b0)
      Upc<=12'b0;
    Upc<=di+ci;
  end
  assign stackIn=di+1;
endmodule

module am2910(clk,di,cc,instr,rld,do,full,pln,mapn,vectn);
  input [11:0] di;
  input clk,cc,rld;
  input [3:0]instr;
  output  full;
  output  [11:0] do;
  output pln,mapn,vectn;
  wire Rzero,plrc,dec,clear,push,pop,respc;
  wire [1:0] selmux;
  wire [11:0] regCounterOut;
  wire [2:0] stackPointerOut;
  wire [11:0] stackIn;
  wire [11:0] upcOut;
  wire [11:0] wordStackOut;
  
  instrDecoder intstrunctionDecoder(instr,cc,RZero,plrc,dec,clear,push,pop,respc,selmux,pln,mapn,vectn);
  
  registerCouner registerCounter(rld,dec,plrc,di,clk,regCounterOut);
  
  stackPointer PointerStack(push,pop,clear,clk,stackPointerOut,full);
  
  wordStack StackWord(stackIn,clk,push,pop,clear,stackPointerOut,wordStackOut);
  
  microUpc UpcMicro(clk,clear,do,1'b1,stackIn,upcOut);
  
  multiplexer Mux(upcOut, wordStackOut, regCounterOut, di, selmux, do);
  
  zeroDetector zeroDec(regCounterOut,Rzero);
  
   
 endmodule
 
 module test_2910;
   reg clk,cc,ci,rld;
   reg [11:0] di;
   reg [3:0] instr;
   wire pln,mapn,vectn;
   wire [11:0] do;
   wire full;
   
   am2910 integrat(clk,di,cc,instr,rld,do,full,pln,mapn,vectn);
  initial
  begin
  #0 clk=1'b0;cc=1'b0;rld=1'b0; di=12'h0; instr=4'h0; ci=1'b1; forever #5 clk=~clk;
  end
  initial 
  begin
  #1000 $finish; 
  end
  
  initial 
  begin
    //test push command 0001_0_x
    #3 di=12'h1FF;
    #8 rld=1'b1; instr=4'h1; cc=1'b0; 
    #17 di=12'h2FF;
    #13  di=12'h3FF;
    #13  di=12'h4FF;
    #13  di=12'h5FF;
    #13  di=12'h6FF;
    #13  di=12'h7FF;
    #13  di=12'h8FF;
    #13  di=12'h9FF;
    #13  di=12'hAFF;
    
    //test pop command 1010_0_x
     #13 rld=1'b1; instr=4'hA; cc=1'b0; 
    
    //test push command 0001_0_x
    #16 di=12'h18F;
    #8 rld=1'b1; instr=4'h1; cc=1'b0; 
    #13 di=12'h28F;
    //test pop command 1010_0_x
    #20 instr=4'hA;
    
    // test 0001_1_x face incrementare micro upc
    #20 instr=4'h1; cc=1'b1;
    
    // test 0010_x_x activate mapn=0;
    #20 instr=4'h2; cc=1'b0;
    //test 0011_1_x 
    #20 instr=4'h3; cc=1'b1;
    // test 0011_0_x
    #20 instr=4'h3; cc=1'b0;
    //test 0100_1_x
    #20 instr=4'h4; cc=1'b1;
    //test 0100_0_x push
    #20 instr=4'h4; cc=1'b0;
    //pop
    #20 rld=1'b1; instr=4'hA; cc=1'b0; 
    //test 0101_1_x push register 
    #20 instr=4'h5; cc=1'b1;
    //pop
    #20 rld=1'b1; instr=4'hA; cc=1'b0; 
    //test 0101_0_x push
    #20 instr=4'h5; cc=1'b0;
    //pop
    #20 rld=1'b1; instr=4'hA; cc=1'b0;
    //test 0110_1_x
    #20 instr=4'h6; cc=1'b1;
    //test 0110_0_x
    #20 instr=4'h6; cc=1'b0;
    //test 0111_1_x
    #20 instr=4'h7; cc=1'b1;
    //test 0111_0_X
    #20 instr=4'h7; cc=1'b0;
    //test 1000_x_x nu m-am asigurat ca R=0 este 0 sau 1
    #20 instr=4'h8; 
    //test 1001_x_x nu m-am asigurat ca R=0 este 0 sau 1
    #20 instr=4'h9;
    //test 1010_1_x
    #20 instr=4'hA; cc=1'b1;
    //test 1010_0_x
    #20 instr=4'hA; cc=1'b0;
    //test 1011_1_x
    #20 instr=4'hB; cc=1'b1;
    //test 1011_0_x
    #20 instr=4'hB; cc=1'b0;
    //test 1100_x_x
    #20 instr=4'hC;
    //test 1101_1_x
    #20 instr=4'hD; cc=1'b1;
    //test 1101_0_x
    #20 instr=4'hD; cc=1'b0;
    //test 1110_x_x
    #20 instr=4'hE;
    // test 1111_1_x nu m-am asigurat ca R=0 este 0 sau 1
    #20 instr=4'hF; cc=1'b1;
    // test 1111_0_x nu m-am asigurat ca R=0 este 0 sau 1
    #20 instr=4'hF; cc=1'b0;
        
    
    
      
  end
endmodule
  





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